1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to semiconductor memory devices of a divided word line structure.
2. Description of the Background Art
A SRAM (Static Random Access Memory) is a semiconductor memory device whose storage data is not lost unless power is turned off. With a recent increase in capacity of a semiconductor memory device, the number of memory cells connected to each word line in such SRAM has been increased.
FIG. 26 is a schematic block diagram of a function of the entire structure of a SRAM and includes only a minimum function block necessary for describing a basic operation of the SRAM, that is, a reading and writing operation. In FIG. 26, a memory cell array 102 includes a circuit structure of a memory cell illustrated as a representative. In practice, memory cell array 102 comprises memory cells each having a shown circuit structure arranged in a matrix of a plurality of rows and columns. A word line WL is provided for each of the plurality of rows and a bit line pair of BitL and BitR is provided for each of the plurality of the columns. Each memory cell is connected to a word line WL and a bit line pair of BitL and BitR respectively corresponding to the row and the column in which the memory cell is disposed.
A basic operation of the SRAM will be described with reference to FIG. 26.
In writing data to a memory cell 200, an external address signal is applied to an address signal input circuit 104, the signal indicative of a location (address) of the memory cell 200 to which data is to be written in memory cell array 102. Address signal input circuit 104 charges a voltage amplitude of the external signal to a voltage amplitude suitable for an internal circuit of this SRAM. For example, if the external signal has a TTL level with its H level (logical high) being 2.2 V and its L level (logical low) being 0.8 V, the voltage amplitude thereof is 1.4 V. If a signal of the internal circuit of the SRAM has an MOS level with its H level being 5 V and its L level being 0 V, its voltage amplitude is 5 V. In such a case, therefore, address signal input circuit 104 changes the voltage amplitude 1.4 V of the external signal to 5 V.
The address signal (hereinafter referred to as an internal address signal) which level has been changed by address signal input circuit 104 is converted into a word line select signal and a bit line pair select signal by an address signal decoding circuit 106.
Memory cell 200 is selected by a word line WL connected thereto attaining a high level potential and a bit line pair of BitL and BitR connected thereto being electrically connected to an internal data bus (not shown) referred to as an I/0 line. The above-described word line select signal and bit line pair select signal are a signal bringing only the potential on the word line WL connected to memory cell 200 to high and a signal electrically connecting the bit line pair of BitL and BitR connected to memory cell 200 with the I/0 line, respectively.
After the selection of memory cell 200 by the word line select signal and the bit line pair select signal, data to be written to memory cell 200 is transferred from the I/O line to the bit lines. The data to be written is supplied to a data signal input circuit 108 as an external signal. Data signal input circuit 108 changes the voltage amplitude of the external data signal to that of the MOS level and applies the level converted signal to a data write circuit 100.
Data write circuit 100 transfers the converted data signal to the I/O line by using a transistor (not shown) with a current drivability enabling a drive of the bit line pair of BitL and BitR. As a result, the bit line pair of BitL and BitR receives the data signal as complementary potentials.
Meanwhile, N channel MOS transistors 210 and 220 are turned on in memory cell 200 in response to a high level potential on the word line WL. Therefore, when the potentials on the bit lines BitL and BitR are at a high level and a low level, respectively, an N channel MOS transistor 240 is rendered conductive in response to a potential increase of a node N1 caused by the high level potential on the bit line BitL and conversely, an N channel MOS transistor 230 is rendered non-conductive in response to a potential drop of a node N2 caused by the low level potential on the bit line BitR. As a result, the potentials transmitted from the I/O line onto the bit lines BitL and BitR are held at nodes N1 and N2. In other words, even after the potential on the word line WL attaining a low level to render transistors 210 and 220 non-conductive, the non-conductive transistor 230 causes the potential at node N1 to remain a high potential (logic high level) transmitted from a power supply Vcc through a resistance element 250, while the conductive transistor 240 causes the potential at node N2 to remain a low potential (.apprxeq.0 V: logic low level) determined by a ratio of a resistance value of a resistance element 260 to an ON resistance value of transistor 240.
The foregoing operation completes data writing in memory cell 200.
In reading data from memory cell 200, an external address signal corresponding to memory cell 200 from which data is to be read is supplied to address signal input circuit 104 as is done in data writing. As a result, the potential on the word line WL connected to memory cell 200 attains a high level to electrically connect the bit line pair BitL and BitR connected to memory cell 200 with the I/O line. The potential increase of the word line WL renders transistors 210 and 220 conductive. As a result, when the potentials at nodes N1 and N2 are respectively at a high level and a low level, for example, the potential on the bit line BitR drops because of current flow from the bit line BitR to ground GND through transistors 210 and 240. Conversely, the potential on the bit line BitL om ,aomtaomed at the high potential at node N1 because no current is generated flowing from bit line BitL to ground GND. That is, complementary potential changes corresponding to the storage data (the potentials maintained at nodes N1 and N2) of the memory cell 200 appear on the bit lines BitL and BitR, respectively.
Differently from data writing, the I/O line is electrically connected to a data amplification circuit 112 in data reading. Therefore, the storage data of memory cell 200 is transferred to data amplification circuit 112 after appearing on the bit lines BitL and BitR.
Data amplification circuit 112 amplifies the potential changes of the bit lines BitL and BitR by amplifying a difference voltage between the potentials on the bit lines BitL and BitR to convert the level of the data signal read from memory cell 200 into a signal level (ordinarily an MOS level) for use in the internal circuit of this SRAM. The level converted data signal is externally output through a transistor (not shown) having a current drivability enabling drive of an external data bus (not shown) and provided in a data signal output circuit 114.
The foregoing operation completes data reading from memory cell 200.
A write control signal input circuit 111 controls data write circuit 100 and data amplification circuit 112 to operate in such a manner as described above. The circuit arrangement of the memory cell shown in FIG. 26 is generally-called high resistive load type, which uses resistance elements 250 and 260 having a large resistance value as loads.
Since in data reading, the potentials on the bit lines BitL and BitR should be fully changed in response to the potentials at nodes N1 and N2, respectively, it is preferable that resistances and capacitances of the bit line pair of BitL and BitR are small.
For example, when high level and low level potentials are maintained at nodes N1 and N2, respectively, the potential on the bit line BitR drops more rapidly in data reading with more current flowing from the bit line BitR to ground GND through transistors 210 and 240. Conversely, when low level and high level potentials are maintained at nodes N1 and N2, respectively, the potential on the bit line BitL drops more rapidly with more current flowing from the bit line BitL to ground GND through transistors 220 and 230. That is, transistors 230 and 240 in the memory cell drive the bit lines BitL and BitR, respectively, in data reading.
Therefore, in order to read out the storage data of memory cell 200 onto the bit line pair of BitL and BitR rapidly and reliably, it is desirable that currents are large, the current which can be drawn by transistor 230 from one bit line BitL to ground GND through transistor 220 and the current which can be drawn by transistor 240 from one bit line BitR to ground GND through transistor 210. However, each transistor size in a memory cell is very small. On the other hand, each bit line length is very large relative to such transistor size. Therefore, resistances and capacitances of the bit lines BitL and BitR are preferably small to allow transistors 230 and 240 in memory cell 200 to rapidly draw some amount of current from the bit lines BitL and BitR, respectively.
Then, the bit line pair of BitL and BitR is formed of metal to have sufficiently small resistances and capacitances.
On the other hand, the word line WL is connected to the gates of transistors 210 and 220 of memory cell 200. In general, a gate of an MOS transistor is formed of a material such as polysilicon having a resistance value larger than that of metal. Therefore, a word line WL formed of metal requires a contact hole for connecting a polysilicon layer constituting the gates of transistors 210 and 220 with a metal layer serving as a word line WL. Such contact hole, however, in general, prevents a semiconductor integrated circuit from being highly integrated and makes a manufacturing process complicated. Then, the word line WL is formed of such a material as polysilicon having a large resistance value than that of metal to be contiguous to the gates of transistors 210 and 220.
However, with a recent increase in capacity of a SRAM, the number of memory cells arranged in each row is increased, which is followed by an increase in length of each word line WL. As a result, a resistance and a capacitance of each word line WL are significantly increased, whereby address signal decoding circuit 106 requires more time to change the potential on the word line WL to a high level.
Transistors 210 and 220 do not rapidly become conductive in memory cell 200 when the word line WL does not rapidly attain a high level potential. As a result, more time is required for the potentials on the bit lines BitL and BitR to be changed in response to the storage data of memory cell 200 in data reading and for the potentials at nodes N1 and N2 to be forced to a level corresponding to external data in data writing. Therefore, such increase in a length of the word line WL increases a time period, i.e. an access time, from a supply of an external address signal to address signal input circuit 104 to data reading from or data writing in a memory cell 200 corresponding to the address signal.
While such problem can be avoided to a certain degree by increasing a size of transistors in address signal decoding circuit to increase a drivability of address signal decoding circuit 106 with respect to the word line WL, it is not possible to increase a size of elements in a semiconductor integrated circuit device without limit. Therefore, the word line WL should be driven by the elements of a limited size provided in address signal decoding circuit 106 irrespective of an increase of the word line length. The problem cannot be resolved in this manner.
As a conventional technique for avoiding such problem as described above, each word line WL is divided into a plurality of sections each section being provided with a decoding circuit for driving the section, which technique is referred to as a divided-word line structure. Such divided-word line technique is disclosed in U.S. Pat. Nos. RE32993 and 4,554,646, for example.
FIG. 27 is a schematic diagram showing the principle of such word line division in a SRAM. The principle of the word line division will be briefly described with reference to FIG. 27.
As shown in FIG. 27(a), a memory cell array 102 is divided into a plurality of blocks in the direction of a row. As shown in FIG. 27(b), each row includes a word line which is divided into individual blocks. Hereinafter, these individually provided word lines are referred to as local word lines. That is, a plurality of local word lines provided corresponding to each row constitutes one word line group in memory cell array 102. Local word line selection is carried out by generating a signal for selecting one local word line in one word line group (hereinafter, referred to as a local word line signal) as shown in FIG. 27(c) by obtaining a logical product of a signal for selecting one block among the plurality of blocks constituting memory cell array 102 (hereinafter referred to also as a Z decoder signal) and a signal for selecting one group among the plurality of word line groups included in memory cell array 102 (hereinafter referred to also as a main word line signal).
As shown in FIG. 27(d), in memory cell array 102, bit line pairs of the corresponding columns of blocks constitute one bit line pair group. One bit line pair is selected from each block by a signal selecting one group among the plurality of bit line pair groups in memory cell array 102.
As shown in FIG. 27(e), out of the memory cells connected to the plurality of the bit line pairs included in the selected one bit line pair group, one memory cell connected to the selected one local word line is selected through such local wide line selection and bit line pair selection. As described above, an address of a memory cell from and in which data is to be read and written is determined by a block address indicative of n-th block to be selected among the plurality of blocks, a row address indicative of an n-th row word line group to be selected among the plurality of word line groups, and a column address indicative of an n-th column bit line pair group of each block to be selected among the plurality of bit line pair groups.
Then, a SRAM of a divided-word line structure includes circuits for generating a local word line signal (hereinafter referred to as a local decoder) by obtaining a logical product of the Z decoder signal and the main word line signal, which circuit is provided for each block.
FIG. 28 is a schematic diagram showing an arrangement of the vicinity of the memory cell array, including a local decoder of the SRAM having a divided-word line structure.
In a memory cell array as shown in FIG. 28, divided n blocks BL0-BL (n-1) are provided with local decoder, groups DEC0-DEC (n-1), respectively. These blocks BL0-BL (n-1) include the same number of local word lines LWL0-LWL (n-1), respectively. Local decoder groups DEC0 -DEC (n-1) include, as local decoders LD0-LD (n-1), logical gates provided corresponding to the local word lines LWL0-LWL (n-1) included in the corresponding blocks BL0-BL (n-1), respectively.
A row decoder 6 is provided for supplying main word line signals to the local decoder groups DEC0-DEC (n-1). A Z decoder 18 is provided for supplying Z decoder signals to the local decoder groups DEC0-DEC (n-1). Row decoder 6 has output signal lines MWL each provided for each row. The signal lines MWL are referred to as main word lines. Z decoder 18 has output signal lines ZL each provided corresponding to each of the local decoder groups DEC0-DEC (n-1). The signal lines ZL are referred to as Z decoder signal lines.
Each of the local decoders LD0-LD (n-1) receives a signal on the corresponding Z decoder signal line ZL and a signal on the main word line MWL of the corresponding row as inputs to selectively generate, onto the corresponding one of the local word lines LWL0-LWL (n-1), a local word line signal for selecting the corresponding local word line.
Row decoder 6 includes logical gate circuits 40 each provided corresponding to each main word line MWL, for example. Upon reception of an external address signal indicative of a row address, one of the logical gate circuits 40 in row decoder 6 outputs, onto the corresponding main word line MWL, a main word line signal for activating the main word line MWL.
Z decoder 18 outputs, onto one of the signal lines ZL, a Z decoder signal for activating the signal line ZL in response to an external address signal indicative of a block address. At this time, both of the potentials on the activated Z decoder signal line and the activated main word line MWL are at a high level. Therefore, with 2-input AND gates being used as the local decoders LD0-LD (n-1), only one local word line connected to one local decoder receiving the potential on the activated main word line MWL and the potential on the activated Z decoder signal line ZL as inputs is brought to a high level. That is, only one local word line receives a local word line signal for activating the local word line.
For the purpose of simplicity, neither bit line pair nor memory cell is shown in FIG. 28.
FIG. 29 shows an actual layout of local decoder groups and divided memory cell array blocks on a semiconductor substrate in such SRAM of a divided-word line structure.
In practice as shown in FIG. 29, n (n is an even number) divided divisional blocks BL0-BL (n-1) of a memory cell array fall into n/2 groups each group including two blocks in view of layout. Then, in each of these n/2 groups, an even-numbered local decoder group provided corresponding to the even-numbered block and an odd-numbered local decoder group provided corresponding to an odd-numbered block located adjacent to the even numbered block are disposed between these two blocks.
Recently proposed in "S. Aizaki et al, IE.sup.3 ISSCC Digest of Technical Papers, pp. 126-127, 1990" and the like is a further division of the row direction divided blocks BL0-BL (n-1) into a plurality of blocks divided in a column direction. FIG. 30 is a circuit diagram showing a schematic arrangement of a main part of a SRAM wherein a memory cell array is divided into 32 blocks of BL0-BL31 in a row direction, each block further divided into 128 sub-blocks of SBL0-SBL127 in a column direction. Each of the blocks BL0-BL31 includes the same number of memory cell columns. Similarly, each of the sub-blocks SBL0-SBL127 includes the same number of memory cell rows.
When each block is further divided into a plurality of sub-blocks in a column direction, row decoder 6 has 128 output signal lines, i.e. 128 main word lines MWL provided corresponding to the sub-block groups SBL0-SBL127. Row decoder 6 includes logical gate circuits 40 provided corresponding to the main word lines MWL, for example. Upon reception of an external address signal indicative of a row address, one of these logical gates 40 applies, to the corresponding main word line MWL, a potential (high level) activating the main word line.
Z decoder 18 has output signal lines, i.e. Z decoder signal lines ZL provided in the same number (m) of the local word lines included in one sub-block for each of the 32 blocks BL0-BL31. Therefore, the plurality of Z decoder signal lines provided corresponding to each of the blocks BL0-BL31 constitute one signal line group ZLG. In response to an external address signal indicative of a block address and an external address signal indicative of a row address, Z decoder 18 supplies, to only one of all the signal lines ZL included in these signal line groups ZLG, a high level potential for activating the one signal line ZL.
Local decoder groups DEC0-DEC31 are provided corresponding to the blocks BL0-BL31, respectively. More specifically, located between each of the odd-numbered blocks BL1, BL3, . . . BL31 and each of the even-numbered blocks BL0, BL2, . . . BL30 adjacent thereto are two local decoder groups corresponding to these two blocks as described above.
The local decoder groups DEC0-DEC31 include logical gate circuits LD0-LD31 as local decoders, respectively, which logical gate circuits are provided for the respective local word lines LWL0-LWL31 included in the corresponding blocks BL0-BL31.
A signal on each main word line MWL is applied in common to all the local decoders LD0-LD31 provided corresponding to the 32 sub-blocks (any of SBL0-SBL127) corresponding to this main word line MWL. A plurality of signal lines included in each Z decoder signal line group ZLG are provided corresponding to a plurality of local word lines in the corresponding block (any of BL0-BL31). Then, the plurality of lines included in each signal line group ZLG are connected in common to 128 local decoders provided corresponding to 128 local word lines corresponding to 128 sub-blocks SBL0-SBL127 included in the corresponding one block.
Therefore, each of the local decoders LD0-LD31 comprises a two-input AND gate, only one local decoder connected to an activated main word line MWL and an activated Z decoder signal line ZL activates the corresponding one local word line. That is, only one local decoder outputs a local word line select signal.
As described above, when a plurality of row direction divided blocks are further divided in a column direction, local word line selection is carried out by row decoder 6 outputting a signal indicating that an n-staged one, out of the sub-blocks, from the top of the drawing including one local word line to be selected and Z decoder 18 outputting a signal indicating an n-numbered block from the left of the drawing including the one local word line to be selected and an n-numbered sub-block from the top including the local word line.
FIG. 31 is a table showing how external address signals are divisionally supplied to row decoder 6 and Z decoder 18 of FIG. 30 in a case of a memory cell array including memory cells arranged in a matrix of 512 rows and 2048 columns. With reference to FIGS. 31 and 30, out of the external address signals indicative of a column direction address of a memory cell to be selected, 5-bit signals Z0-Z4 indicative of block addresses are input to Z decoder 18 and 6-bit signals Y0-Y5 indicative of column addresses in a block are input to a column decoder (not shown in FIG. 30). Out of the external address signals indicative of a row direction address of a memory cell to be selected, more significant 7-bit signals X2-X8 are input to row decoder 6 and less significant 2-bit signals X0 and X1 are input to Z decoder 18.
In such a case, row decoder 6 decodes the 7-bit signals X2-X8 to output 2.sup.7 -bit (=128) signals X0-X127 one of which signals being at a high level. As a result, only one of the 128 main word lines MWL is activated. Z decoder 18 decodes a total of 7-bit signals including 5-bit block address signals Z0-Z4 and two-bit row address signals X0 and X1 to output 2-bit (=32.times.4) X decoder signals ZX0-ZX127 only one of which signals being at a high level.
In case of a memory cell array including 512 memory cell rows, each of the sub-blocks SBL0-SBL127 includes four local word lines. Therefore, output of the above-described 128-bit signals ZX0-ZX127 by Z decoder 18 activates one of four signal lines ZL included in one of the 32 signal line groups ZLG provided corresponding to 32 blocks BL0-BL31.
The column decoder decodes the 6-bit signals Y0-Y6 to output 2.sup.6 -bit (=64) signals one of which signals is at a high level. In case of a memory cell array including 2048 memory cell columns, each of the blocks BL0-BL31 includes 64 bit line pairs and therefore, each of the 64-bit signals selects one bit line pair in each of the blocks BL0-BL31.
FIG. 32 is a logical circuit diagram showing an example of an actual arrangement of a local decoder. An arrangement of a conventional local decoder will be described with reference to FIG. 32.
In the following description, in n blocks BL0-BL (n-1) obtained by dividing the memory cell array in a row direction, local word lines included in even-numbered blocks and local word lines included in odd-numbered blocks are represented as LWL (2j) and LWL (2j+1), respectively (j=0, 1, . . . , (n-2)/2). Similarly, local decoders provided corresponding to the odd-numbered blocks and local decoders provided corresponding to the even-numbered blocks are represented as LD (2j) and LD (2j+1), respectively.
FIG. 32 shows, as a representative, two local decoders LD (2j) and LD (2j+1) arranged adjacent to each other in actual layout.
Each of the conventional local decoders LD (2j) and LD (2j+1) includes, for example, a two-input NAND gate 800 receiving a signal on the corresponding main word line MWL and a signal on the corresponding Z decoder signal line ZL and an inverter 810 for inverting the output of NAND gate 800. The output signal from inverter 810 is supplied to the corresponding local word line LWL (2j) or LWL (2j+1).
Operation of the local decoders shown in FIG. 32 will be described with reference to FIG. 33. FIG. 33 is a table of truth values of the logical circuit shown in FIG. 32.
As can be seen from FIG. 33, in each of the local decoders LD (2j) and LD (2j+1), the output potential (that is, the potentials on the corresponding local word lines LWL (2j) and LWL (2j+1)) of inverter 810 attains a high level in response to NAND gate 800 attaining a low level output potential only when both of the potentials on the corresponding main word line MWL and the corresponding Z decoder signal line ZL are at a high level. However, when at least one of the potentials on the corresponding main word line MWL and the corresponding Z decoder signal line ZL is at a low level, the output potential of NAND gate 800 is fixed to a high level, whereby the output potential of inverter 810 is at a low level. Therefore, the corresponding local word lines LWL (2j) and LWL (2j+1) are not activated unless both of the potentials on the corresponding main word line MWL and Z decoder signal line ZL attain a high level.
FIG. 34 is a circuit diagram showing a specific circuit arrangement of NAND gate 800 and inverter 810 of FIG. 32 relative to a single local decoder. Now, an arrangement of a conventional local decoder will be described in more detail with reference to FIG. 34.
In each local decoder, NAND gate 800 includes a P channel MOS transistor 800a and N channel MOS transistors 800b and 800c connected in series to each other between power supply Vcc and ground GND and a P channel MOS transistor 800d provided between power supply Vcc and a node between transistors 800a and 800b. The gates of transistors 800a and 800b are connected to the Z decoder signal line ZL and the gates of transistors 800c and 800d are connected to the main word line MWL. Inverter 810 includes a P channel MOS transistor 810a and an N channel MOS transistor 810b connected in series to each other between power supply Vcc and ground GND. The node between transistors 810a and 810b is connected to the local word line LWL (2j) or LWL (2j+1).
The gates of transistors 810a and 810b are connected to the node between transistors 800a and 800b.
When the potential on the main word line MWL is at a low level, while transistor 800d is turned on, transistor 800c is turned off, so that the gate potential of transistors 810a and 810b attains a high level irrespective of ON/OFF states of transistors 800a and 800b. Therefore, when the potential on the main word line MWL is at a low level, the local word line LWL (2j) or LWL (2j+1) connected to inverter 810 attains a low level, that is, it is activated irrespective of the potential level of the signal line ZL.
Conversely, when the potential on the main word line MWL is at a high level, transistor 800c is turned on, while transistor 800d is turned off, whereby the gate potential of transistors 810a and 810b is changed according to ON/OFF states of transistors 800a and 800b. That is, when transistor 800a is rendered conductive in response to a low level potential on the signal line ZL, the gate potential of transistors 810a and 810b attains a high level. Conversely, when transistor 800b is rendered conductive in response to a high level potential on the signal line ZL, the gate potential of transistors 810a and 810b attains a low level. Therefore, in case of the main word line MWL attaining a high level potential, the potential on the local word line LWL (2j) or LWL (2j+1) connected to inverter 810 attains a high level, that is, it is activated only when the potential on the Z decoder signal line ZL is at a high level.
In FIG. 34, a numeral in parenthesis put beside each element represents a gate width of the element in .mu.m.
As described above, each local decoder for use in a semiconductor memory device of a divided-word line structure is arranged as shown in FIG. 34 in order to obtain the logical product of a signal on the corresponding main word line and a signal on the corresponding Z decoder signal line. More specifically, each local decoder requires a total of 6 elements including two transistors constituting an inverter and four transistors constituting an NAND gate.
As can be seen from FIG. 28 and FIG. 30, the semiconductor memory device of a divided-word line structure requires the same number of local decoders as that of local word lines. For example, in a case where each of the sub-blocks SBL0-SBL127 includes four local word lines in FIG. 30, 2.sup.14 (=4 lines.times.128 sub-blocks.times.32 blocks) local decoders are required to make the total area of the local decoders equivalent to the total area of as many as 6.times.2.sup.14 MOS transistors.
As described in the foregoing, local decoders occupying a large area of a semiconductor memory device of a divided-word line structure make it difficult to reduce a chip area of a semiconductor memory device and to increase a memory capacity of the same.
In other words, in order to increase a storage capacity of a semiconductor memory device without increasing a chip area, more area of a semiconductor substrate available for use for a memory cell array is required by reducing an area occupied by other circuits than the memory cell array, thereby increasing the number of memory cells arranged on one chip. However, it is difficult to reduce an area of such peripheral circuits because even a single local decoder includes six elements. This fact makes a local decoder of a conventional arrangement another factor preventing an increase of a capacity of a semiconductor memory device.
In addition, as shown in FIGS. 28 and 30, the Z decoder signal line is formed extending in a column direction of a memory cell array also on a semiconductor substrate. Therefore, in a memory cell array divided both in a row direction and a column direction as shown in FIG. 30, a large number of Z decoder signal lines are arranged in a column direction between the respective odd-numbered blocks BL1, BL3, . . . BL31 and the even-numbered blocks BL0, BL2, . . . BL30 disposed adjacent thereto. For example, in FIG. 32, wherein each of the sub-blocks SBL0-SBL127 includes four local word lines, a total of 8 Z decoder signal lines are arranged in a column direction between an even-numbered block and an odd-numbered block adjacent to each other. As a result, the total of a row direction width of wiring layers forming the Z decoder signal lines reaches a high sum, resulting in an increase in the total width of the local decoders and the Z decoder signal lines provided corresponding thereto on the semiconductor substrate. Thus, a conventional semiconductor memory device of a divided-word line structure has an increased row direction width of other circuits than a memory cell array.
As described above, conventional semiconductor memory device of a divided-word line structure involves difficulty in increasing a capacity of a semiconductor memory device and reducing a chip area because of not only the number of elements of each local decoder but also the number of Z decoder signal lines.